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Overview of the CPU Module
Power Mac G4/667 and G4/733 systems use the new CPU module which equips PowerPC 7450 (Vgor or G4+) processor. Figure 1 and 2 are the front and the back view of the new CPU module. The CPU module consists of a PowerPC processor, L3 cache SRAMs, various power supply circuits and a high density connector to the logic board.
Fig. 1 Front View of MPC7450 CPU Module
Fig. 2 Back View of MPC7450 CPU Module
(1) MPC7450 (Vgor or "G4 Plus") Processor
According to the PPC Checker, my CPU is PowerPC 7450 (Vgor) Rev 2.0. The marking on CPU die is,
XPC7450
RX733PD
73K51S
DMN0106
Maybe, the last line means it was shipped at the beginning of February (6th week of 2001).
The CPU is set to 1.8V I/O and 1.5V L3 bus.
(2) L3 cache SRAM
L3 cache SRAMs (located on both front and back side) are Samsung K7D403671M-HC25, 4Mbit DDR SRAM. The L3RT bits in the L3CR register (L3CR[22:23]) are set to "00". So the CPU surely drives the SRAM as MSUG2 DDR SRAM. It is the reason that the 1/4 speed L3 does not cause the performance loss.
However, "HC25" speed grade of K7D403671M chip is 4ns in cycle time. So, it should work up to 250MHz.
(3) CPU Core Power Supply
Core supply voltage of MPC7450 is controlled CS5165 buck controller located on the back side. Default voltage was set to 1.9V by the registers on the module.
(4) L2 SRAM Core Power Supply
Core supply voltage of L3 SRAM is generated on the CPU module by EZ1583CM voltage regulator. The default setting was 2.5V.
(5) L2 bus Power Supply
Another EZ1583CM generates L3 bus I/O voltage.
(6) CPU Module Connector
The connector to the logic board is the same 300pin connector with original sawtooth system.
Speed Setting of CPU Module
(1) Bus Ratio
PLL_CFG code is set by the registers on the back side of the CPU module. Figure 2 shows the location of the PLL_CFG registers and Fig. 3 is the expanded view of them. By placing a 1k ohm register, each bit is set to "0". Typical bus ratio settings are shown in Table 1. The Complete PLL_CFG code is written in MPC7450 hardware specification.
Fig. 3 PLL_CFG registers
Table 1 Bus Ratio Settings
| PLL_CFG[0:3] |
Bus Ratio |
Comments |
| 1010 |
4x |
|
| 0111 |
4.5x |
|
| 1011 |
5x |
G4/667 default |
| 1001 |
5.5x |
G4/733 default |
| 1101 |
6x |
|
| 0101 |
6.5x |
|
| 0010 |
7x |
|
| 0001 |
7.5x |
|
(2) CPU core supply voltage (Vdd)
VID code is set by the registers on the back side of the CPU daughter card.
Figure 2 shows the location of VID registers and Fig. 4 is the expanded view of them. By placing a 0 ohm register, each bit is set to "0". The Typical core supply voltage settings are shown in Table 2. Complete VID code is written in CS5165 datasheet.
Fig. 4 VID registers
Table 2 Core Supply Voltage Settings
| VID[0:4] |
Vdd [V] |
Comments |
| 00010 |
1.70 |
|
| 11100 |
1.75 |
|
| 01100 |
1.80 |
|
| 10100 |
1.85 |
|
| 00100 |
1.90 |
default |
| 11000 |
1.95 |
|
| 01000 |
2.00 |
|
Overclocking Results
I have successfuly overclocked G4/733 to 867MHz. A screenshot of Apple System Profiler is shown in Fig. 5. Some benchmarking results are shown in Table 3.
Fig. 5 Screenshot of Apple System Profiler
Table 3 Benchmarking results
Mac OS 9.1, VM on, GeForce2 MX v1.1.1
| MacBench 5.0 |
|
| CPU |
2263 |
| FPU |
2251 |
| CineBench 2000 |
|
| Shading (C4D) |
6.98 |
| Shading (OpenGL) |
8.82 |
| Raytrace (Single) |
10.54 |
| AltiVec Fractal Demo |
[MFlops] |
| |
3193.1 |
| G4TimeDemo |
[fps] |
| Millions, Hardware, Amazing |
79.3 |
Quake3 Demo v1.11, 32bit, DEMO1
(Lightmap lighting, Geometric detail high, Texture detail 1 notch from max, Texture filter - bilinear, All Game Options ON)
[Corrected results w/clean config file sent 4/3/2001] |
[fps] |
| 640x480 with sound |
81.6 |
| 800x600 with sound |
76.9 |
| 1024x768 with sound |
56.9 |
| 640x480 without sound |
97.0 |
| 800x600 without sound |
87.2 |
| 1024x768 without sound |
57.1 |
| 640x480 Locki 1.3 with sound |
140.4 |
| 640x480 Locki 1.3 without sound |
192.3 |
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