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G4 (Mirrored Drive Doors) Processor Module Speed Settings
By Michiro Isobe
Published 8/26/2002
(revised 10/8/2002 for 133->167MHz Bus Speed Mod)


    Disclaimer/Warning: This page is for reference information only. Performing modifications or other work inside your Mac will void your Apple warranty, may cause damage to your computer or result in personal injury (blah, blah blah...) Any modifications to your CPU module may result in permanent damage requiring expensive parts replacement, failures or data loss. The resistors on these modules are very small surface mount devices, requiring very delicate soldering skills beyond the capability of most end users. The author and site publishers DO NOT recommend attempting any of the mods listed here.

Speed Settings of the Processor Module

PowerMac G4 (Mirrored Drive Doors) uses new processor module that differs from Quicksilver. Figure 1 and 2 are the front and the back view of the new processor module. The CPU module consists of two MPC7455 processors, L3 cache SRAMs, various power supply circuits and a megarray connector to the logic board.

Front View of Processor Module
Fig. 1  Front View of Processor Module

Back View of Processor Module
Fig. 2  Back View of Processor Module

(1) Bus Ratio
There are two set of PLL_CFG registers which are corresponding to each processors. The one is on front side shown in Fig.1 and the other is on the back side shown in Fig.2. Figuar 3 is the expanded view of them. By placing a 1k ohm register, each bit is set to "0". Typical bus ratio settings are shown in Table 1. The Complete PLL_CFG code is written in MPC7455 hardware specification.

Front PLL_CFG Registers Back PLL_CFG Registers
(a) Front PLL_CFG array (b) Back PLL_CFG array
Fig. 3 PLL_CFG registers

Table 1 Bus Ratio Settings
PLL_CFG[0:3] PLL_EXT Bus Ratio Comments
1101 0 6x Dual 1GHz default
0101 0 6.5x Dual 867MHz default
0010 0 7x  
0001 0 7.5x Dual 1.25GHz default
1100 0 8x  
0111 1 9x  

(2) Core supply voltage (Vdd)
Core supply voltage (Vdd) is controlled with LTC1709 switching regulator. The VID code is set by the registers on the back side of the processor module. Figure 2 shows the location of VID registers and Fig. 4 is the expanded view of them. By placing a 47 ohm register (they're marked 471, so assuming 470ohm), each bit is set to "0". The Typical core supply voltage settings are shown in Table 2. Complete VID code is written in LT1709 datasheet.

VID Registers
Fig. 4 VID registers

Table 2 Core Supply Voltage Settings
VID[0:4] Vdd [V] Comments
11100 1.70  
01100 1.75  
10100 1.80  
00100 1.85 default
11000 1.90  
01000 1.95  
10000 2.00  

Currently I am evaluating 1.16GHz overclocking. As for 1.16GHz OCing, I am suffering on cooling. Built-In large (12cm sq.) fan seems not to be able to cool upper part of a heat sink. If things go well, I will send some benchmarking results.

Although I have not been able to confirm yet, there are some other interesting points

  1. The FSB clock looks software controlled
    (Update - see below for hardware mods for 133Mhz to 167MHz bus mods for the 867MHz model)
  2. There is soldering pattern corresponding to the unknown (IEEE1394b?) connector of eBay prototype.

Best Regards,
Michiro Isobe


Bus Speed Mods (133 to 167MHz) for Dual 867 Model: *Update* - There's now an english page on the 167MHz bus speed mod. *FYI* One reader commented on Oct. 18th that comparing the french to english pages looks like the english page has some resistor values switched. Use the French page resistor info until this is corrected/verified.
(From the 10/8/2002 www.xlr8yourmac.com news page)
There's been a thread in the forums here on trying to change the bus speed on DDR G4 867 models from 133 to 166MHz (as the Dual 1GHz and Dual 1.25GHz models are - requires PC2700 memory of course, not the PC2100 ram that ships in the dual 867s). Lionel of Macbidouille (French site) sent a link to info and photos on the modification. (Here's a link to a google English translated page link. Altavista's babelfish also has language translators.)
Note boosting the bus speed overclocks the CPU beyond 1GHz, so you need to also modify the resistor settings to reduce the bus/cpu ratio (multiplier) per above info in the table.


 
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