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Apple G4 Sawtooth CPU Module Speed Settings
By Michiro Isobe
Published: 11/30/1999
(Updated 6/22/2000 for 133MHz Bus Info/Tests)
(Updated 1/27/2001 for Firmware/Timebase info)
(Updated 4/20/2001 for OS X issues with overclocked bus speeds)
(Updated 12/26/2001 for comments on OS X 10.1.2 solving time-base problem)

    Disclaimer/Warning: This page is for reference information only. Performing modifications or other work inside your Mac will void your Apple warranty, may cause damage to your computer or result in personal injury. Any modifications to your CPU module may result in permanent damage requiring expensive parts replacement, data loss or personal injury. The resistors on these modules are very small surface mount devices, requiring very delicate soldering skills   beyond the capability of most end users. The author and site publishers DO NOT recommend attempting any of the mods listed here.

Dual G4/500 CPU Module Speed Settings: Thanks to "Zack" for the photos of a Dual G4/500 module at this page which shows the Bus/CPU ratio resistor areas. (added 12/14/2000)

6/22/2000 Update: 133MHz Bus Speed Notes: Michiro Isobe wrote that he'd found a way to run the G4 at 133MHz bus speeds.

The following is from his MaC CPU Upgrade report:

"Power Mac G4/450 rev.A
Stock 450/225/100MHz bus
Running 466/233/133MHz bus

By using two 128MB PC133 CL2 DIMMs (, 133MHz bus can be running. The timebase problem in my previous report (here) was solved by firmware tweaking.

The MacBench 5 results show only CopyBits operations are improved (by ~40%) with the bus overclocking.
Michiro Isobe"

Michiro also sent Stream, Memory Watch and GaugePro test results.

GaugePro Results:
133MHz bus speed memory bandwidth
(Note: My G4/500 (100Mhz bus) reports 234 MB/sec (max) w/GaugePro 1.02/OS 9.04)

Stream Results:
Stream results - 133mhz bus

Memory Watch Results:
Memory Watch tests

133MHz Bus Mod Timebase/Firmware Info:
Update: 12/26/2001 Michiro Isobe wrote that OS X 10.1.2 solved the time-base problem noted earlier (below):

    " Today, I found that Mac OS X 10.1.2 has fixed the time-base problem of bus-overclocked sawtooth. Although Apple System Profiler has shown fixed 100MHz bus clock, the clock works normally and you can fix it by Open Firmware tweaking.
    Best Regards,
    Michiro Isobe"

(Original info added 1/27/2001) Michiro Isobe wrote:

1. G4 (Gigabit Ethernet) and G4 Cube have no time-base problem.

2. The method of "firmware tweaking" for old sawtooth models.

Old G4 models (before G4 Gigabit and Cube) have some time-base problem, which the clock run faster (or slower) when the bus clock changed faster (or slower) than default of 100MHz. This is caused by timing routines of Mac OS, such as TickCount, Microseconds and UpTime, calculate time using actual bus clock and some ##fixed## values supposing 100MHz (99.6MHz exactly) bus. So, we must change these constants when change the bus clock.
I changed these constants using "NVRAMRC" OpenFirmware script. The NVRAMRC is stored in nvram and is performed at boot sequence.

How to edit and store the NVRAMRC for 133MHz bus

(1) Boot by holding down "Cmd" + "Opt" + "O" + "F" keys to enter the OpenFirmware terminal.
(2) Enter the NVRAMRC editor. (<return> shows you should type "return" key)

(3) Type following script exactly (including space).
    " /" select-dev<return>
    7efdc44 " clock-frequency" get-my-property 2drop !<return>
    " /cpus/PowerPC,G4@0" select-dev<return>
    1fca0554 " clock-frequency" get-my-property 2drop !<return>
    7efdc44 " bus-frequency" get-my-property 2drop !<return>
    1fbf711 " timebase-frequency" get-my-property 2drop !
(4) Type "Cntl" + "C" to exit NVRAMRC editor.
(5) Save the script
(6) To enable the NVRAMRC, type this command.
       setenv use-nvramrc? true<return>

(7) Reboot with new timebase constant.

If you fail to edit the NVRAMRC or need to return to the 100MHz bus, you can clear the changes by resetting the nvram, booting by holding down "Cmd" + "Opt" + "P" + "R". (This Apple article also explains how to reset the NVRAM.)

In many cases, 133MHz bus does not work. If it seems to work, it is stable with very limited conditions.
Michiro ISOBE"

(NOTE: Michiro later noted that at 133MHz, only 2 dimm slots were usable (even with 133mhz RAM.) Also see below for comments on problems in OS X with overclocked bus speeds. [Solved by OS X 10.1.2 update he later said.] Remember that 133MHz bus speeds require PC133 RAM *and* a mod to the CPU module to lower the bus/cpu ratio - otherwise the CPU will be so overclocked it will not boot. (I.E. - a G4/450 module is set to 4.5x ratio for the original 100MHz bus - at 133MHz the CPU will be trying to run 600MHz, which will not even boot. And for 450 and 500Mhz G4s - there is no setting that for those CPU speeds exactly, and the closest settings run 466MHz and 533MHz, which may not be reliable since it's overclocking the CPU beyond its rated speeds.)

OS X Issues with 133MHz Bus Speed Mod: (added 4/20/2001)

"[updated] Mac OS 9.1 resolves the timebase problem of all sawtooth models without Open Firmware tweaking. The only problem is Apple System Profiler still recognizes the bus clock to be 100MHz and displays incorrect machine speed.

(Mac OS X) Mac OS X has the same time-base problem with the original sawtooth system. Unfortunately, OS X detects Open Firmware tweaking to "timebase-frequency" and refuses to boot. Currently no solution is found.
[UPDATE: Michiro Isobe wrote that OS X 10.1.2 solved the time-base problem present with earlier OS X versions.]

Best Regards,
Michiro Isobe "

Bus Ratio, Core Supply, L2 Signal Level and Bus Clock Details
of the Apple Sawtooth G4 System:

(1) Bus Ratio Controls:

PLL_CFG signals are set by registers on the back side of the CPU daughter card.
(See Fig1.jpg and Fig2.jpg for photos identifying these)
Placing a 1k ohm register sets each bit to "0"

  • PLL_CFG[0]   R7
  • PLL_CFG[1]   R9
  • PLL_CFG[2]   R11
  • PLL_CFG[3]   R13

The PLL_CFG code is shown at Table 14 in the following PDF document.
(These links from 2000 may no longer be valid over time.)
(Update - a reader noted the link at

(2) CPU Core Supply Voltage (Vdd):

VID signals are set by registers on the back side of the CPU daughter card.
(See Fig1.jpg and Fig3.jpg for photos identifying these)
Placing a 0 ohm register set each bit to "0"

  • VID4   R37
  • VID3   R38
  • VID2   R39
  • VID1   R44
  • VID0   R78

The VID code is the same with Yosemite based system. Please consult the voltage identification table of this PDF document
(UPDATE: CherrySemi was acquired by ON Semiconductor, so the URL above is now invalid.
Default setting was 2.1V

(3) L2 Signal Level:

L2 signal level was specified to be 2.5V by the PPC7400 design docs. But it can be adjusted a little by changing a register at the back side of the CPU daughter card. (See Fig1.jpg and Fig4.jpg for photos identifying these)

    L2OVdd = 1.260 x (R51 + R52)/R51
    Default: R51 = 124 ohm, R52 = 124 ohm.

(4) Bus Clock Configuration:

Bus and AGP/PCI clock can be changed by the registers at the back side of the motherboard. (See Fig5.jpg and Fig6.jpg for photos identifying these)

But, I found that the bus overclocing also make the time base run fast. So this modification is nonsense. If you try the bus overclocking, you must find the source of time base and supply a clock independently.

  • FS0   R435
  • FS1   R434
  • FS2   R433
  • SSON  R432

There is frequency table in this PDF document. sg500.pdf [link revised 1/20/2001]

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